? semiconductor components industries, llc, 2008 august, 2008 ? rev. 1 1 publication order number: nb3n3011/d nb3n3011 3.3 v 100 mhz / 106.25 mhz pureedge clock generator with lvpecl differential output description the nb3n3011 is a fibre channel clock generator and uses a 26.5625 mhz crystal to synthesize 106.25 mhz or a 25 mhz crystal to synthesize 100 mhz. the nb3n3011 has excellent <1 ps phase jitter performance over the 637 khz ? 10 mhz integration range. the nb3n3011 is packaged in an 8 ? pin 4.4 mm x 3.0 mm tssop, making it ideal for use in systems with limited board space. features ? pureedge clock family provides accuracy and precision ? one differential lvpecl output ? crystal oscillator interface designed for fundamental mode 18 pf parallel resonant crystal (25 mhz or 26.5625 mhz) ? output frequency: 106.25 mhz (26.5625 mhz crystal) or 100 mhz (25 mhz crystal) ? vco range: 760 mhz ? 950 mhz ? rms phase jitter @ 100 mhz, using a 25 mhz crystal (637 khz ? 10 mhz): 0.29 ps (typical) ? rms phase noise at 106.25 mhz phase noise: offset noise power 100 hz ? 108 dbc/hz 1 khz ? 122 dbc/hz 10 khz ? 135 dbc/hz 100 khz ? 135 dbc/hz ? 3.3 v power supply ? ? 40 c to 85 c ambient operating temperature ? these are pb ? free devices* figure 1. logic diagram phase detector charge pump n = 8 m = 32 crystal oscillator q q x in x out vco 850 mhz w/26.5625 mhz ref. 25 mhz or 26.5625 mhz lvpecl output 100 mhz or 106.25 mhz *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. marking diagram a = assembly location y = year ww = work week = pb ? free package tssop ? 8 dt suffix case 948s http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. ordering information 311 yww a
nb3n3011 http://onsemi.com 2 figure 2. pinout (top view) q 1 2 3 4 8 7 6 5 vcca vee xout xin vcc q nc nb3n3011 table 1. pin description pin symbol type description 1 v cca power positive analog power supply pin. connected to v cc with filter components (see figure 8). 2 v ee power negative supply pin. 3 x out input crystal input (out). 4 x in input crystal input (in). 5 nc unused no connect. 6 q output inverted differential output. typically terminated with 50 to v cc ? 2.0 v. 7 q output noninverted differential output. typically terminated with 50 to v cc ? 2.0 v. 8 v cc power positive digital core power supply pin. connected to 3.3 v. table 2. attributes characteristic value esd protection human body model machine model > 6 kv > 200 v moisture sensitivity (note 1) pb ? free pkg, tssop ? 8 level 3 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 4150 meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d. table 3. maximum ratings symbol parameter value unit v cc supply voltage 4.6 v v i inputs ? 0.5 to v cc + 0.5 v i o output current continuous surge 50 100 ma ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm 142 103 c/w t stg storage temperature ? 65 to 150 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability.
nb3n3011 http://onsemi.com 3 table 4. power supply dc characteristics, (v cc = 3.3 v 5%, t a = ? 40 c to 85 c ) symbol parameter conditions min typ max unit v cc core supply voltage 3.135 3.3 3.465 v v cca analog supply voltage 3.135 3.3 3.465 v i cca analog supply current included in i ee 19 23 ma i ee power supply current 27 31 ma note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. table 5. lvpecl dc characteristics, (v cc = 3.3 v 5%, t a = ? 40 c to 85 c ) symbol parameter conditions min typ max unit v oh output high voltage (note 2) v cc ? 1.4 v cc ? 0.9 v v ol output low voltage (note 2) v cc ? 2.0 v cc ? 1.7 v v swing peak ? to ? peak output voltage swing 0.6 0.75 1.0 v note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. outputs terminated with 50 to v cc ? 2.0 v. see figures 4 and 12. table 6. pin characteristics symbol parameter conditions min typ max unit c in input capacitance 4 pf table 7. crystal characteristics (fundamental mode 18 pf parallel resonant crystal ) parameter conditions min typ max unit frequency 24 30 mhz equivalent series resistance (esr) 50 shunt capacitance 7.0 pf table 8. ac characteristics, (v cc = 3.3 v 5%, t a = ? 40 c to 85 c (note 4)) symbol parameter conditions min typ max unit f out output frequency 24 mhz ? 30 mhz crystal (typ. 25 mhz ? 26.5625 mhz) 96 100/106.25 120 mhz t jit( ? ) rms phase jitter (random) (note 3) 106.25 mhz; integration range: 637 khz ? 10 mhz 0.29 ps 100 mhz; integration range: 637 khz ? 10 mhz 0.29 t r /t f output rise/fall time 20% to 80% (see figure 7) 275 600 ps odc output duty cycle (see figure 6) 48 52 % note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. please refer to the phase noise plot. 4. output terminated with 50 to v cc ? 2.0 v. see figures 4 and 12.
nb3n3011 http://onsemi.com 4 figure 3. typical phase noise at 106.25 mhz noise power (dbc) offset frequency (hz) parameter measurement information scope q 2 v clock outputs 20% 80% 80% 20% pulse width phase noise mask offset frequency phase noise plot lvpecl figure 4. output load ac test circuit (split power supply) figure 5. rms phase jitter figure 6. output duty cycle/pulse width/period figure 7. output rise/fall time 50 50 v cc v ee ? 1.3 v 0.165 v z = 50 z = 50 f 1 f 2 t period noise power odc t pw t period rms area under the masked phase noise plot t r t f v swing q q q q q
nb3n3011 http://onsemi.com 5 application information power supply filtering the nb3n3011 is a mixed analog/digital product, and as such, it exhibits some sensitivities that would not necessarily be seen on a fully digital product. analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. the nb3n3011 also generates sub ? nanosecond output edge rates, and therefore, a good power supply bypassing scheme is a must. the nb3n3011 provides separate power supplies for the digital circuitry (v cc ) and the internal pll (v cca ). the simplest form of noise isolation is a power supply filter on the v cca pin. figure 8 illustrates a typical power supply filter scheme. the parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the pll. the purpose of this design technique is to try and isolate the high switching noise of the digital outputs from the relatively sensitive internal analog phase ? locked loop. the power supply filter and bypass schemes discussed in this section should be adequate to eliminate power supply noise ? related problems in most designs. crystal oscillator input interface the nb3n3011 features an integrated crystal oscillator to minimize system implementation costs. the oscillator circuit is a parallel resonant circuit and thus, for optimum performance, a parallel resonant crystal should be used. as the oscillator is somewhat sensitive to loading on its inputs, the user is advised to mount the crystal as close to the nb3n3011 as possible to avoid any board level parasitics. surface mount crystals are recommended, but not required. figure 9 illustrates a parallel resonant crystal with its associated load capacitors. the capacitor values shown were determined using a 26.5625 mhz, 18 pf parallel resonant crystal and were chosen to minimize the ppm error. capacitor values can be adjusted slightly for different board layouts to optimize accuracy. figure 8. power supply filtering 3.3 v 0.01 f 0.01 f 10 f 10 v cc v cca figure 9. crystal input interface c1 33 pf x1 18 pf c2 27 pf parallel crystal x out x in application schematic figure 10 shows a schematic example of the nb3n3011. an example of lvpecl termination is shown in this schematic. additional lvpecl termination approaches are shown in the and8020 application note. in this example, an 18 pf parallel resonant 26.5625mhz crystal is used for generating 106.25 mhz output frequency. the c1 = 27 pf and c2 = 33 pf are recommended for frequency accuracy. for different board layout, the c1 and c2 values may be slightly adjusted for optimizing frequency accuracy. figure 10. typical application schematic r2 10 33 pf r6 82.5 + ? u1 1 2 3 4 8 7 6 5 r3 133 x1 q c5 c4 c1 27 pf r5 133 v cca v cc z o = 50 z o = 50 r4 82.5 v cc 18 pf c3 0.01 f 10 f v cc v cca c2 v ee 0.1 q nc q q x out x in v cc v cc = 3.3 v
nb3n3011 http://onsemi.com 6 pc board layout example figure 11 shows a representative board layout for the nb3n3011. there exists many different potential board layouts and the one pictured is but one. the crystal x1 footprint shown in this example allows installation of either surface mount hc49s or through ? hole hc49 package. the footprints of other components in this example are listed in table 9. there should be at least one decoupling capacitor per power pin. the decoupling capacitors should be located as close as possible to the power pins. the layout assumes that the board has clean analog power ground plane. the important aspect of the layout in figure 11 is the low impedance connections between v cc and gnd for the bypass capacitors. combining good quality general purpose chip capacitors with good pcb layout techniques will produce effective capacitor resonances at frequencies adequate to supply the instantaneous switching current for the nb3n3011 outputs. it is imperative that low inductance chip capacitors are used. it is equally important that the board layout not introduce any of the inductance saved by using the leadless capacitors. thin interconnect traces between the capacitor and the power plane should be avoided and multiple large vias should be used to tie the capacitors to the buried power planes. fat interconnect and large vias will help to minimize layout induced inductance and thus maximize the series resonant point of the bypass capacitors. the voltage amplitude across the crystal is relatively small. it is imperative that no actively switching signals cross under the crystal as crosstalk energy coupled to these lines could significantly impact the jitter of the device. table 9. footprint table reference size c1, c2 0402 c3 0805 c4, c5 0603 r2 0603 figure 11. pc board layout c2 c1 figure 12. typical termination for output driver and device evaluation (see application note and8020/d ? termination of ecl logic devices.) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v cc ? 2.0 v ordering information device package shipping ? nb3n3011dtg tssop8 4.4 mm (pb ? free) 100 units / rail NB3N3011DTR2G tssop8 4.4 mm (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nb3n3011 http://onsemi.com 7 package dimensions tssop ? 8 case 948s ? 01 issue c dim min max min max inches millimeters a 2.90 3.10 0.114 0.122 b 4.30 4.50 0.169 0.177 c --- 1.10 --- 0.043 d 0.05 0.15 0.002 0.006 f 0.50 0.70 0.020 0.028 g 0.65 bsc 0.026 bsc l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. terminal numbers are shown for reference only. 6. dimension a and b are to be determined at datum plane -w-. seating plane pin 1 1 4 85 detail e b c d a g l 2x l/2 ? u ? s u 0.20 (0.008) t s u m 0.10 (0.004) v s t 0.076 (0.003) ? t ? ? v ? ? w ? 8x ref k ident k 0.19 0.30 0.007 0.012 s u 0.20 (0.008) t detail e f m 0.25 (0.010) ??? ??? k1 k jj1 section n ? n j 0.09 0.20 0.004 0.008 k1 0.19 0.25 0.007 0.010 j1 0.09 0.16 0.004 0.006 n n on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 nb3n3011/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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